#include "plat_clock.h"
/*
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 *  install, copy or use the software.
 *
 *  Intel Open Source License 
 *
 *  Copyright (c) 2002 Intel Corporation 
 *  All rights reserved. 
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are
 *  met:
 * 
 *      Redistributions of source code must retain the above copyright
 *  notice, this list of conditions and the following disclaimer.
 *      Redistributions in binary form must reproduce the above copyright
 *  notice, this list of conditions and the following disclaimer in the
 *  documentation and/or other materials provided with the distribution.
 *      Neither the name of the Intel Corporation nor the names of its
 *  contributors may be used to endorse or promote products derived from
 *  this software without specific prior written permission.
 *  
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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 */

 
uint8_t DVFS_SwitchCoreFreq(uint32_t coreFreq, uint32_t sysBusFreq)
{
	/*
	 * TODO : add all supported frequencies, for now support 13 & 104 only
     *        add core voltage switching to min value based on freq
     */
	switch (coreFreq) {
		case 13:
			if (sysBusFreq != 13) {
				return 1;
			}
			
			CCCR = CCCR_CPDIS | CCCR_A;
			asm volatile (
			   "mcr p14,0,%0,c6,c0,0\n\t"
			   :
			   : "r" (0x2)
			   );
			// check that core PLL was disabled
			while ((CCSR & CCSR_CPDIS_S) == 0);
			
			return 0;
		case 104:
			if (sysBusFreq != 104) {
				return 1;
			}
			
			CCCR = CCCR_L(8) | CCCR_2N(2) | CCCR_A ;
			asm volatile (
			   "mcr p14,0,%0,c6,c0,0\n\t"
			   :
			   : "r" (0xb)
			   );
			// wait until core pll locks
			while ((CCSR & CCSR_CPLCK) == 0);
			
			return 0;
		default:
			return 1;
	}
}
